Invention Grant
US08402251B2 Selecting configuration memory address for execution circuit conditionally based on input address or computation result of preceding execution circuit as address
失效
根据前面执行电路的输入地址或计算结果作为地址，有条件地选择执行电路的配置存储器地址
- Patent Title: Selecting configuration memory address for execution circuit conditionally based on input address or computation result of preceding execution circuit as address
- Patent Title (中): 根据前面执行电路的输入地址或计算结果作为地址，有条件地选择执行电路的配置存储器地址
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Application No.: US12544122Application Date: 2009-08-19
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Publication No.: US08402251B2Publication Date: 2013-03-19
- Inventor: Takashi Yoshikawa , Shigehiro Asano
- Applicant: Takashi Yoshikawa , Shigehiro Asano
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2008-289397 20081112
- Main IPC: G06F9/38
- IPC: G06F9/38
Abstract:
A semiconductor device includes a first circuit that executes a first calculation, a second circuit that includes a first storage unit therein and executes a second calculation, a controller that outputs a first address for specifying a first execution circuit for the first calculation and a second execution circuit for the second calculation, to the first circuit and the second circuit, and controls input of data into the first circuit, and a bus that transfers a result of the first calculation executed by the first circuit to the second circuit, wherein the result of the first calculation can be conditionally used as an address for specifying the second execution circuit.
Public/Granted literature
- US20100122071A1 SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD Public/Granted day:2010-05-13
Information query
