Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit. The multi-power rail status indicating logic may include a synchronous assertion/asynchronous de-assertion multi-power rail status signal generator that receives the clock signal and the asynchronous multi-power rail voltage stability signal, and in response to of the assertion of the asynchronous multi-power rail voltage stability signal, synchronizes the asynchronous multi-power rail voltage stability signal with the clock signal to assert the multi-power rail status signal.