A signal processor, which includes: a signal receiving section for receiving signals encoded under a predetermined code rule; a rule violation detecting section for detecting code rule violation included in the signals received by the signal receiving section; an error range specifying section for specifying a range in which an error bit is included out of a bit string which constitutes the signals on the basis of a position of the code rule violation detected by the rule violation detecting section; and an error correcting section for correcting one error bit in the range specified by the error range specifying section so that the code rule violation detected by the rule violation detecting section is eliminated.