Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
- Patent Title (中): 半导体装置及其制造方法
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Application No.: US12510858Application Date: 2009-07-28
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Publication No.: US08404547B2Publication Date: 2013-03-26
- Inventor: Yuichiro Kitajima , Hideo Yoshino
- Applicant: Yuichiro Kitajima , Hideo Yoshino
- Applicant Address: JP
- Assignee: Seiko Instruments Inc.
- Current Assignee: Seiko Instruments Inc.
- Current Assignee Address: JP
- Agency: Brinks Hofer Gilson & Lione
- Priority: JP2008-195014 20080729
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a high withstanding voltage is required, is etched, and the drain diffusion layer is formed so as to spread into a surface region of a semiconductor substrate located below a region in which the LOCOS oxide film is thinned. As a result, end portions of the drain diffusion layer are covered by an offset diffusion layer, whereby electric field concentration occurring in a region of a lower portion of the drain diffusion layer can be relaxed.
Public/Granted literature
- US20100025764A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2010-02-04
Information query
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