Invention Grant
US08404550B2 Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement
有权
通过增加掺杂剂约束,包括高k金属栅极堆叠的PFET晶体管的性能增强
- Patent Title: Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement
- Patent Title (中): 通过增加掺杂剂约束,包括高k金属栅极堆叠的PFET晶体管的性能增强
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Application No.: US12905383Application Date: 2010-10-15
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Publication No.: US08404550B2Publication Date: 2013-03-26
- Inventor: Thilo Scheiper , Sven Beyer , Andy Wei , Jan Hoentschel
- Applicant: Thilo Scheiper , Sven Beyer , Andy Wei , Jan Hoentschel
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102009047304 20091130
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.
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