Invention Grant
- Patent Title: Method for fabricating an isolation structure
- Patent Title (中): 隔离结构的制造方法
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Application No.: US12774219Application Date: 2010-05-05
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Publication No.: US08404561B2Publication Date: 2013-03-26
- Inventor: Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
- Applicant: Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.
Public/Granted literature
- US20100291751A1 METHOD FOR FABRICATING AN ISOLATION STRUCTURE Public/Granted day:2010-11-18
Information query
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