Invention Grant
US08405154B2 Low cost transistors using gate orientation and optimized implants
有权
低成本晶体管采用栅极取向和优化的植入
- Patent Title: Low cost transistors using gate orientation and optimized implants
- Patent Title (中): 低成本晶体管采用栅极取向和优化的植入
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Application No.: US13167538Application Date: 2011-06-23
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Publication No.: US08405154B2Publication Date: 2013-03-26
- Inventor: Kamel Benaissa , Greg C. Baldwin , Shaofeng Yu , Shashank S. Ekbote
- Applicant: Kamel Benaissa , Greg C. Baldwin , Shaofeng Yu , Shashank S. Ekbote
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/70
- IPC: H01L21/70

Abstract:
An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.
Public/Granted literature
- US20110248347A1 LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS Public/Granted day:2011-10-13
Information query
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