Invention Grant
- Patent Title: Semiconductor device comprising multilayer interconnect structure with overlapping vias
- Patent Title (中): 半导体器件包括具有重叠通孔的多层互连结构
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Application No.: US12982064Application Date: 2010-12-30
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Publication No.: US08405224B2Publication Date: 2013-03-26
- Inventor: Kazuo Itoh
- Applicant: Kazuo Itoh
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2009-120613 20090519
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
A semiconductor device having a multilayer interconnect structure allowing heat in an interconnect layer at an intermediate level to be effectively dissipated is provided. A lower-layer interconnect (13), an intermediate interconnect (23), an upper-layer interconnect (33), a first contact via (15) formed to electrically connect the lower-layer interconnect (13) to the intermediate interconnect (23), and a second contact via (25) formed to electrically connect the intermediate interconnect (23) to the upper-layer interconnect (33) are provided. When viewed from above, the first and second contact vias (15, 25) both have a rectangular shape with their long sides extending in the same direction, and overlap with each other.
Public/Granted literature
- US20110089574A1 SEMICONDUCTOR DEVICE Public/Granted day:2011-04-21
Information query
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