Invention Grant
- Patent Title: Three-dimensional integrated circuits with protection layers
- Patent Title (中): 具有保护层的三维集成电路
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Application No.: US13437533Application Date: 2012-04-02
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Publication No.: US08405225B2Publication Date: 2013-03-26
- Inventor: Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Hung-Jung Tu , Ku-Feng Yang
- Applicant: Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Hung-Jung Tu , Ku-Feng Yang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/31 ; H01L25/00
Abstract:
A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.
Public/Granted literature
- US20120187576A1 Three-Dimensional Integrated Circuits with Protection Layers Public/Granted day:2012-07-26
Information query
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