Invention Grant
US08405427B2 Multilevel slicer 失效
多层切片机

Multilevel slicer
Abstract:
A circuit design configured to process a differential input signal is provided. A first floating capacitor ladder is configured to receive the positive of the differential input signal and is connected to a first switched capacitor network through phase one controlled switches. A second floating capacitor ladder configured to receive the negative of the differential input signal and is connected to a second switched capacitor network through other phase one controlled switches. A reference resistor ladder is connected to the first switched capacitor network through phase two controlled switches to provide voltage references and connected to the second switched capacitor network through other phase two controlled switches to provide the voltage references. Response to controlling the switches, the first floating capacitor ladder is configured to output first voltage thresholds to a comparator array and the second floating capacitor ladder is configured to output second voltage thresholds to the comparator array.
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