A circuit configuration having a detection unit designed to generate an output signal that is representative of a load current of a transistor switch, depending on an input signal that is representative of the load current of the transistor switch. The detection unit includes a temperature compensation unit that is designed to take into account the temperature of the transistor switch. The detection unit further includes a delay unit that is designed to delay the detection of the input signal until a prescribed switch-on time period, relative to a switch-on procedure of the transistor switch, has passed. The detection unit is designed in an application-specific integrated circuit.