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US08406039B2 Low-leakage power supply architecture for an SRAM array 有权
SRAM阵列的低漏电电源架构

Low-leakage power supply architecture for an SRAM array
Abstract:
A method of forming an integrated circuit structure includes providing a chip; forming a static random access memory (SRAM) cell including a transistor on the chip; and forming a bias transistor configured to gate a power supply voltage provided to the SRAM cell on the chip. The bias transistor and the transistor of the SRAM cell are formed simultaneously.
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