Invention Grant
US08406049B2 Nonvolatile semiconductor memory device and writing method thereof
失效
非易失性半导体存储器件及其写入方法
- Patent Title: Nonvolatile semiconductor memory device and writing method thereof
- Patent Title (中): 非易失性半导体存储器件及其写入方法
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Application No.: US13020401Application Date: 2011-02-03
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Publication No.: US08406049B2Publication Date: 2013-03-26
- Inventor: Hidefumi Nawata
- Applicant: Hidefumi Nawata
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-164265 20100721
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04

Abstract:
A control circuit is configured to execute a writing operation for giving a second threshold voltage distribution to a plurality of memory cells formed along one word line. In the writing operation, the control circuit performs a writing operation by executing a voltage applying operation in memory cells to be given the second threshold voltage distribution. While the control circuit executes a voltage applying operation in memory cells to be maintained in an erased state, thereby moving a first threshold voltage distribution to a positive direction to obtain a third threshold voltage distribution representing the erased state.
Public/Granted literature
- US20120020160A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF Public/Granted day:2012-01-26
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