Invention Grant
- Patent Title: Semiconductor memory device with improved ECC efficiency
- Patent Title (中): 具有提高ECC效率的半导体存储器件
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Application No.: US13351266Application Date: 2012-01-17
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Publication No.: US08406054B2Publication Date: 2013-03-26
- Inventor: Noboru Shibata , Kazunori Kanebako
- Applicant: Noboru Shibata , Kazunori Kanebako
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-338241 20071227
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h≦n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells.
Public/Granted literature
- US20120113717A1 SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED ECC EFFICIENCY Public/Granted day:2012-05-10
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