The present invention provides a semiconductor memory device, the voltage divider circuit comprises a data line sense amplifier and an input output data sensing circuit. The data line sense amplifier receives a data line signal pair and senses the data line signal pair in a first timing period to generate a first output data and a second output data, wherein, the first output data and the second output data are complementary. The input output data sensing circuit receives at least one reference output data and one of the first and the second output data. The input output data sensing circuit generates a sensed data by comparing voltage levels of the reference output data and the one of the first and the second output data in a second timing period, wherein the voltage level of the reference output data is a pre-determined voltage level.