In certain embodiments, a circuitincludes a dividing device configured to divide a transmission bit sequence into a first bit sequence and a second bit sequence, bits adjacent to each other in the transmission bit sequence being separated by a bit time. The circuit includes a first device configured to generate first sampled values by sampling at a sampling rate a first fundamental wave that is based on the first bit sequence, and includes a second device configured to generate second sampled values by sampling at the sampling rate a second fundamental wave that is based on the second bit sequence, the second fundamental wave being shifted relative to the first fundamental wave by a time period. The circuit includes a summator configured to sum the first sampled values of the first fundamental wave and the second sampled values of the second fundamental wave to form an output value sequence.