Invention Grant
- Patent Title: Counter circuit and solid-state imaging device
- Patent Title (中): 计数电路和固态成像装置
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Application No.: US13179009Application Date: 2011-07-08
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Publication No.: US08406370B2Publication Date: 2013-03-26
- Inventor: Kazuki Hizu
- Applicant: Kazuki Hizu
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-232346 20101015
- Main IPC: H03K23/00
- IPC: H03K23/00

Abstract:
According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting operation of a sub counter of a next stage after finishing a counting operation in a sub counter of a local stage.
Public/Granted literature
- US20120093277A1 COUNTER CIRCUIT AND SOLID-STATE IMAGING DEVICE Public/Granted day:2012-04-19
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