Invention Grant
US08407432B2 Cache coherency sequencing implementation and adaptive LLC access priority control for CMP
失效
缓存一致性排序实现和CMP自适应LLC访问优先级控制
- Patent Title: Cache coherency sequencing implementation and adaptive LLC access priority control for CMP
- Patent Title (中): 缓存一致性排序实现和CMP自适应LLC访问优先级控制
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Application No.: US11173917Application Date: 2005-06-30
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Publication No.: US08407432B2Publication Date: 2013-03-26
- Inventor: Zhong-Ning Cai , Krishnakanth V. Sistla , Yen-Cheng Liu , Jeffrey D. Gilbert
- Applicant: Zhong-Ning Cai , Krishnakanth V. Sistla , Yen-Cheng Liu , Jeffrey D. Gilbert
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Mnemoglyphics, LLC
- Agent Lawrence M. Mennemeier
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.
Public/Granted literature
- US20070005909A1 Cache coherency sequencing implementation and adaptive LLC access priority control for CMP Public/Granted day:2007-01-04
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