In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a first half of a second ten-bit message to generate a first partial sum and a carry-over bit. The second non-reconfigurable adder adds a second half of the first ten-bit message, a second half of the second ten-bit message, and the carry-over bit to generate a second partial sum. A ten-bit sum is then generated by combining the first and second partial sums.