Invention Grant
- Patent Title: Method for decreasing polysilicon gate resistance in a carbon co-implantation process
- Patent Title (中): 降低碳共同注入工艺中多晶硅栅极电阻的方法
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Application No.: US13339417Application Date: 2011-12-29
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Publication No.: US08409975B1Publication Date: 2013-04-02
- Inventor: Liujiang Yu
- Applicant: Liujiang Yu
- Applicant Address: CN Shanghai
- Assignee: Shanghai Huali Microelectronics Corporation
- Current Assignee: Shanghai Huali Microelectronics Corporation
- Current Assignee Address: CN Shanghai
- Agency: Renner, Otto, Boisselle & Sklar, LLP
- Priority: CN201110265267 20110908
- Main IPC: H01L21/425
- IPC: H01L21/425

Abstract:
A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.
Public/Granted literature
- US20130065372A1 METHOD FOR DECREASING POLYSILICON GATE RESISTANCE IN A CARBON CO-IMPLANTATION PROCESS Public/Granted day:2013-03-14
Information query
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