Invention Grant
- Patent Title: Substrate with embedded patterned capacitance
- Patent Title (中): 基板与嵌入式图案电容
-
Application No.: US13345227Application Date: 2012-01-06
-
Publication No.: US08410536B2Publication Date: 2013-04-02
- Inventor: John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
- Applicant: John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
- Applicant Address: US SC Simpsonville
- Assignee: Kemet Electronics Corporation
- Current Assignee: Kemet Electronics Corporation
- Current Assignee Address: US SC Simpsonville
- Agency: Perkins Law LLC
- Agent Joseph T. Guy
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01G4/005

Abstract:
A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
Public/Granted literature
- US20120106032A1 SUBSTRATE WITH EMBEDDED PATTERNED CAPACITANCE Public/Granted day:2012-05-03
Information query
IPC分类: