Invention Grant
US08410542B2 Charge-trapping nonvolatile memory devices having gate structures therein with improved blocking layers
有权
电荷捕获其中具有栅极结构的非易失性存储器件具有改进的阻挡层
- Patent Title: Charge-trapping nonvolatile memory devices having gate structures therein with improved blocking layers
- Patent Title (中): 电荷捕获其中具有栅极结构的非易失性存储器件具有改进的阻挡层
-
Application No.: US12938006Application Date: 2010-11-02
-
Publication No.: US08410542B2Publication Date: 2013-04-02
- Inventor: Dong-Chul Yoo , Byong-Ju Kim , Han-Mei Choi , Ki-Hyun Hwang
- Applicant: Dong-Chul Yoo , Byong-Ju Kim , Han-Mei Choi , Ki-Hyun Hwang
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2009-0105257 20091103
- Main IPC: H01L29/792
- IPC: H01L29/792

Abstract:
Nonvolatile memory devices include a tunnel insulating layer on a substrate and a charge storing layer on the tunnel insulating layer. A charge transfer blocking layer is provided on the charge storing layer. The charge transfer blocking layer is formed as a composite of multiple layers, which include a first oxide layer having a thickness of about 1 Å to about 10 Å. This first oxide layer is formed directly on the charge storing layer. The charge transfer blocking layer includes a first dielectric layer on the first oxide layer. The charge transfer blocking layer also includes a second oxide layer on the first dielectric layer and a second dielectric layer on the second oxide layer. The first and second dielectric layers have a higher dielectric constant relative to the first and second oxide layers, respectively. The memory cell includes an electrically conductive electrode on the charge transfer blocking layer.
Public/Granted literature
- US20110101438A1 Nonvolatile Memory Devices Having Gate Structures Therein with Improved Blocking Layers Public/Granted day:2011-05-05
Information query
IPC分类: