Invention Grant
- Patent Title: Semiconductor memory device
- Patent Title (中): 半导体存储器件
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Application No.: US13224814Application Date: 2011-09-02
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Publication No.: US08411487B2Publication Date: 2013-04-02
- Inventor: Mitsuru Nakura , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
- Applicant: Mitsuru Nakura , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Nixon & Vanderhye, P.C.
- Priority: JP2010-214009 20100924
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.
Public/Granted literature
- US20120075911A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2012-03-29
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