Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array. Applying a plurality of voltage potentials to the memory cells may further include applying a third voltage potential to a respective word line of the array, wherein the word line may be spaced apart from and capacitively to a body region of the memory cell that may be electrically floating and disposed between the first region and the second region. Applying a plurality of voltage potentials to the memory cells may further include applying a fourth voltage potential to a third region of the memory cell via a respective carrier injection line of the array.