Invention Grant
US08412983B2 Memory test circuit, semiconductor integrated circuit, and memory test method
有权
记忆测试电路，半导体集成电路和存储器测试方法
- Patent Title: Memory test circuit, semiconductor integrated circuit, and memory test method
- Patent Title (中): 记忆测试电路，半导体集成电路和存储器测试方法
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Application No.: US12585898Application Date: 2009-09-28
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Publication No.: US08412983B2Publication Date: 2013-04-02
- Inventor: Keigo Nakatani
- Applicant: Keigo Nakatani
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value.
Public/Granted literature
- US20100023809A1 Memory test circuit, semiconductor integrated circuit, and memory test method Public/Granted day:2010-01-28
Information query
