Invention Grant
- Patent Title: Method for manufacturing semiconductor package
- Patent Title (中): 制造半导体封装的方法
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Application No.: US13007444Application Date: 2011-01-14
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Publication No.: US08415200B2Publication Date: 2013-04-09
- Inventor: Mi Sun Hwang , Keung Jin Sohn , Eung Suek Lee , Myung Sam Kang
- Applicant: Mi Sun Hwang , Keung Jin Sohn , Eung Suek Lee , Myung Sam Kang
- Applicant Address: KR Suwon, Gyunggi-do
- Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee Address: KR Suwon, Gyunggi-do
- Agency: Blakely Sokoloff Taylor & Zafman LLP
- Priority: KR10-2010-0098850 20101011
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
Disclosed herein is a method for manufacturing a semiconductor package which uses a base member 120 in which a first metal layer 113, a barrier layer 115, and a second metal layer 117 are stacked on both surface thereof in sequence based on an adhesive member 111 to simultaneously manufacture two printed circuit boards through a single sheet process, thereby making it possible to improve manufacturing efficiency; electrically connects a semiconductor chip 300 to a printed circuit board through a solder bump 250, thereby making it possible to implement a high-density package substrate; and forms a metal post 140 instead of a through hole to required in an interlayer circuit connection, thereby making it possible to reduce costs required in the processing/plating of the through hole.
Public/Granted literature
- US20120088334A1 METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE Public/Granted day:2012-04-12
Information query
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