Invention Grant
US08415217B2 Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor
有权
对形成电容器的非易失性存储器(NVM)的栅极堆叠进行构图
- Patent Title: Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor
- Patent Title (中): 对形成电容器的非易失性存储器(NVM)的栅极堆叠进行构图
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Application No.: US13077563Application Date: 2011-03-31
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Publication No.: US08415217B2Publication Date: 2013-04-09
- Inventor: Bradley P. Smith , Mehul D. Shroff
- Applicant: Bradley P. Smith , Mehul D. Shroff
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Joanna G. Chiu; James L. Clingan, Jr.
- Main IPC: H01L21/8242
- IPC: H01L21/8242 ; H01L21/336 ; H01L21/44

Abstract:
A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region.
Public/Granted literature
- US20120252178A1 PATTERNING A GATE STACK OF A NON-VOLATILE MEMORY (NVM) WITH FORMATION OF A CAPACITOR Public/Granted day:2012-10-04
Information query
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