Invention Grant
- Patent Title: Semiconductor device with a pillar region and method of forming the same
- Patent Title (中): 具有柱区域的半导体器件及其形成方法
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Application No.: US11765252Application Date: 2007-06-19
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Publication No.: US08415737B2Publication Date: 2013-04-09
- Inventor: Berinder P. S. Brar , Wonill Ha
- Applicant: Berinder P. S. Brar , Wonill Ha
- Applicant Address: US CA San Jose
- Assignee: Flextronics International USA, Inc.
- Current Assignee: Flextronics International USA, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.
Public/Granted literature
- US20070298559A1 Vertical Field-Effect Transistor and Method of Forming the Same Public/Granted day:2007-12-27
Information query
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