Invention Grant
US08415751B2 Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain
有权
通过在源极和漏极中使用III-V半导体夹层来降低N沟道晶体管的接触电阻的方法
- Patent Title: Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain
- Patent Title (中): 通过在源极和漏极中使用III-V半导体夹层来降低N沟道晶体管的接触电阻的方法
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Application No.: US12982083Application Date: 2010-12-30
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Publication No.: US08415751B2Publication Date: 2013-04-09
- Inventor: Niloy Mukherjee , Gilbert Dewey , Marko Radosavljevic , Robert S. Chau , Matthew V. Metz
- Applicant: Niloy Mukherjee , Gilbert Dewey , Marko Radosavljevic , Robert S. Chau , Matthew V. Metz
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent David L. Guglielmi
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/205 ; H01L21/203
Abstract:
A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.
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