Invention Grant
- Patent Title: High-voltage BJT formed using CMOS HV processes
- Patent Title (中): 使用CMOS HV工艺形成高压BJT
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Application No.: US12750503Application Date: 2010-03-30
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Publication No.: US08415764B2Publication Date: 2013-04-09
- Inventor: Tao-Wen Chung , Po-Yao Ke , Wei-Yang Lin , Shine Chung
- Applicant: Tao-Wen Chung , Po-Yao Ke , Wei-Yang Lin , Shine Chung
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L27/082
- IPC: H01L27/082

Abstract:
An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.
Public/Granted literature
- US20100301453A1 High-Voltage BJT Formed Using CMOS HV Processes Public/Granted day:2010-12-02
Information query
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