Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).