Invention Grant
- Patent Title: Lead frame for semiconductor package
- Patent Title (中): 半导体封装引线框架
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Application No.: US13047803Application Date: 2011-03-15
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Publication No.: US08415779B2Publication Date: 2013-04-09
- Inventor: Tzu Ling Wong , Chee Seng Foong , Kai Yun Yow
- Applicant: Tzu Ling Wong , Chee Seng Foong , Kai Yun Yow
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Priority: MYPI2010001643 20100413
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
A lead frame for providing electrical interconnection to an Integrated Circuit (IC) die. The lead frame includes a die support area for receiving and supporting the IC die and a plurality of leads surrounding the die support area. A plurality of interconnect receiving portions is formed in the die support area. The interconnect receiving portions are for providing electrical interconnection to first bumps on a bottom surface of the IC die. The leads are for providing electrical interconnection to second bumps on a surface of the IC die, the second bumps surrounding the first bumps.
Public/Granted literature
- US20110248390A1 LEAD FRAME FOR SEMICONDUCTOR PACKAGE Public/Granted day:2011-10-13
Information query
IPC分类: