Invention Grant
- Patent Title: Three-dimensionally integrated semicondutor device and method for manufacturing the same
- Patent Title (中): 三维集成半导体器件及其制造方法
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Application No.: US12991149Application Date: 2009-05-07
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Publication No.: US08415789B2Publication Date: 2013-04-09
- Inventor: Masamichi Ishihara
- Applicant: Masamichi Ishihara
- Applicant Address: JP Fukuoka
- Assignee: Kyushu Institute of Technology
- Current Assignee: Kyushu Institute of Technology
- Current Assignee Address: JP Fukuoka
- Agency: McGlew and Tuttle, P.C.
- Priority: JP2008-123446 20080509
- International Application: PCT/JP2009/001999 WO 20090507
- International Announcement: WO2009/136496 WO 20091112
- Main IPC: H01L23/34
- IPC: H01L23/34

Abstract:
A wiring substrate has, on each of opposite faces thereof, connection pad portions to which various circuit elements are connected, and wiring traces for connecting the connection pad portions. The wiring substrate also has a through wiring portion for establishing mutual connection between the connection pad portions and the wiring traces on the front face and those on the back face. A post electrode component is formed such that it includes a plurality of post electrodes supported by a support portion. A semiconductor chip is attached to the back face of the wiring substrate, and is connected to the connection pad portions on the back face. After the post electrode component is fixed to and electrically connected to the wiring traces at predetermined positions, and resin sealing is performed, the support portion is separated so as to expose end surfaces of the post electrodes or back face wiring traces connected thereto. Another circuit element is disposed on the front face of the wiring substrate, and is connected to the connection pad portions on the front face.
Public/Granted literature
- US20110062584A1 THREE-DIMENSIONALLY INTEGRATED SEMICONDUTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2011-03-17
Information query
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