Invention Grant
- Patent Title: PLL circuit
- Patent Title (中): PLL电路
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Application No.: US13241549Application Date: 2011-09-23
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Publication No.: US08415998B2Publication Date: 2013-04-09
- Inventor: Mitsushi Tabata
- Applicant: Mitsushi Tabata
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Fujitsu Patent Center
- Priority: JP2010-279341 20101215
- Main IPC: H03L7/07
- IPC: H03L7/07

Abstract:
A PLL circuit, has a phase comparator for comparing phases of a reference clock and a feedback clock, and outputting a phase comparison signal indicating the phase difference; a charge pump circuit, which, during a time period corresponding to the phase difference, outputs a first charge pump current and a second charge pump current; a loop filter, having a capacitor storing electric charge based on the first and second charge pump currents, which generates a control voltage due to stored electric charge; an oscillator generating an output clock at a frequency according to the control voltage; a frequency divider frequency-dividing the output clock and outputs the feedback clock; and a charge pump adjustment circuit, which, when in a locked state, adjusts current quantity of the first or the second charge pump current such that the phase difference is suppressed, according to the phase difference indicated by the phase comparison signal.
Public/Granted literature
- US20120154000A1 PLL CIRCUIT Public/Granted day:2012-06-21
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