Invention Grant
- Patent Title: N channel JFET based digital logic gate structure
- Patent Title (中): 基于N沟道JFET的数字逻辑门结构
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Application No.: US13098918Application Date: 2011-05-02
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Publication No.: US08416007B1Publication Date: 2013-04-09
- Inventor: Michael J Krasowski
- Applicant: Michael J Krasowski
- Applicant Address: US DC Washington
- Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
- Current Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
- Current Assignee Address: US DC Washington
- Agent Robert H. Earp, III
- Main IPC: H03K17/687
- IPC: H03K17/687
Abstract:
An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.
Information query
IPC分类:
