Invention Grant
- Patent Title: Method and apparatus for efficient modulo multiplication
- Patent Title (中): 用于有效模乘的方法和装置
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Application No.: US12216896Application Date: 2008-07-11
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Publication No.: US08417756B2Publication Date: 2013-04-09
- Inventor: Eran Pisek , Thomas M. Henige
- Applicant: Eran Pisek , Thomas M. Henige
- Applicant Address: KR Suwon-Si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-Si
- Main IPC: G06F7/38
- IPC: G06F7/38

Abstract:
A method of a hardware based Montgomery reduction contemplates preparing a table comprising a plurality of sets of values of 2K+i (mod n), 2K+i+1 (mod n) and (2K+i+2K+i+1)(mod n), where i=0 to M−2, n is a modulo number, K is an integer, and M is a number of significant bits in a binary Y; selecting one of the values within one of the plurality of sets of the table in dependence upon a value of two neighboring bits Yi+1,i of the binary Y; adding two neighboring selected values and calculating the modulo value of the sum value with the modulo number n; repeatedly adding two neighboring calculated modulo values and calculating the modulo value of the intermediate sum of the two neighboring calculated modulo values until only a single calculated module value is obtained; and setting the single value as the Montgomery representation.
Public/Granted literature
- US20090144353A1 Method and apparatus for efficient modulo multiplication Public/Granted day:2009-06-04
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