Invention Grant
- Patent Title: Device and method for calculating a multiplication addition operation and for calculating a result of a modular multiplication
- Patent Title (中): 用于计算乘法加法运算和计算乘法运算结果的装置和方法
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Application No.: US11554174Application Date: 2006-10-30
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Publication No.: US08417760B2Publication Date: 2013-04-09
- Inventor: Wieland Fischer
- Applicant: Wieland Fischer
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Schiff Hardin LLP
- Priority: DE102005051772 20051028; DE102006025569 20060601
- Main IPC: G06F7/52
- IPC: G06F7/52

Abstract:
For calculating a result of a modular multiplication with long operands, at least the multiplicand is divided into at least three shorter portions. Using the three shorter portions of the multiplicand, the multiplier and the modulus, a modular multiplication is performed within a cryptographic calculation, wherein the portions of the multiplicand, the multiplier and the modulus are parameters of the cryptographic calculation. The calculation is performed sequentially using the portions of the multiplicand and using an intermediate result obtained in a previous calculation, until all portions of the multiplicand are processed, to obtain the final result of the modular multiplication. The calculation of an intermediate result is performed using a multiplication addition operation, in which MMD operations and updating operations are performed sequentially, and short auxiliary registers and short result registers are used.
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