Invention Grant
- Patent Title: Delay fault testing computer product, apparatus, and method
- Patent Title (中): 延迟故障测试计算机产品,设备和方法
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Application No.: US12778329Application Date: 2010-05-12
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Publication No.: US08418009B2Publication Date: 2013-04-09
- Inventor: Tsutomu Ishida
- Applicant: Tsutomu Ishida
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2009-120958 20090519
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A computer-readable medium stores therein a program that causes a computer to execute acquiring for each chip, first delay values of paths in chips manufactured using circuit information concerning a circuit-under-test; building a function model representing a delay value of a path, based on the first delay values for the path and the circuit information; calculating a second delay value of a path included in and having the same configuration in each chip, using a built function model and the circuit information; comparing for each chip, a given calculated second delay value and the first delay value of a given path having a configuration identical to that of the path for which the given second delay value has been calculated; determining based on a comparison result, the given path to be a path that includes a delay error occurring irregularly according to chip; and outputting a determination result.
Public/Granted literature
- US20100299096A1 DELAY FAULT TESTING COMPUTER PRODUCT, APPARATUS, AND METHOD Public/Granted day:2010-11-25
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