Invention Grant
US08418106B2 Techniques for employing retiming and transient simplification on netlists that include memory arrays
失效
对包含存储器阵列的网表进行重新定时和瞬态简化的技术
- Patent Title: Techniques for employing retiming and transient simplification on netlists that include memory arrays
- Patent Title (中): 对包含存储器阵列的网表进行重新定时和瞬态简化的技术
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Application No.: US12872490Application Date: 2010-08-31
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Publication No.: US08418106B2Publication Date: 2013-04-09
- Inventor: Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
- Applicant: Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Yudell Isidore Ng Russell PLLC
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.
Public/Granted literature
- US20120054702A1 Techniques for Employing Retiming and Transient Simplification on Netlists That Include Memory Arrays Public/Granted day:2012-03-01
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