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US08418120B2 Solutions for netlist reduction for multi-finger devices 有权
针对多手指设备的网表减少的解决方案

Solutions for netlist reduction for multi-finger devices
Abstract:
A computer-implemented method for performing a layout extraction for a multi-fingered semiconductor device is disclosed. The method reduces the netlist for the device and the number of device fingers by identifying a set of device common nodes, and combining a plurality of parasitic elements in the device to form a set of representative parasitic elements which are connected to respective device common nodes. In one embodiment, the method includes combining the parasitic elements of at least one device common node into a single representative parasitic element which is representative of the original parasitic elements.
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