Invention Grant
US08418156B2 Two-stage commit (TSC) region for dynamic binary optimization in X86
有权
X86中动态二进制优化的两阶段提交(TSC)区域
- Patent Title: Two-stage commit (TSC) region for dynamic binary optimization in X86
- Patent Title (中): X86中动态二进制优化的两阶段提交(TSC)区域
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Application No.: US12639251Application Date: 2009-12-16
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Publication No.: US08418156B2Publication Date: 2013-04-09
- Inventor: Cheng Wang , Youfeng Wu
- Applicant: Cheng Wang , Youfeng Wu
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: G06F9/45
- IPC: G06F9/45

Abstract:
Generally, the present disclosure provides systems and methods to generate a two-stage commit (TSC) region which has two separate commit stages. Frequently executed code may be identified and combined for the TSC region. Binary optimization operations may be performed on the TSC region to enable the code to run more efficiently by, for example, reordering load and store instructions. In the first stage, load operations in the region may be committed atomically and in the second stage, store operations in the region may be committed atomically.
Public/Granted literature
- US20110145551A1 TWO-STAGE COMMIT (TSC) REGION FOR DYNAMIC BINARY OPTIMIZATION IN X86 Public/Granted day:2011-06-16
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