Invention Grant
- Patent Title: Method for manufacturing circuit pattern-provided substrate
- Patent Title (中): 制造电路图形衬底的方法
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Application No.: US12364314Application Date: 2009-02-02
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Publication No.: US08418359B2Publication Date: 2013-04-16
- Inventor: Ryohei Satoh , Koji Nakagawa , Eiji Morinaga , Reo Usui , Kenji Tanaka , Satoru Takaki , Kenichi Ebata , Hiroshi Sakamoto
- Applicant: Ryohei Satoh , Koji Nakagawa , Eiji Morinaga , Reo Usui , Kenji Tanaka , Satoru Takaki , Kenichi Ebata , Hiroshi Sakamoto
- Applicant Address: JP Tokyo
- Assignee: Asahi Glass Company, Limited
- Current Assignee: Asahi Glass Company, Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JPP.2006-210835 20060802; JPP.2007-193567 20070725
- Main IPC: H05K3/02
- IPC: H05K3/02 ; H05K3/10

Abstract:
A method for manufacturing a circuit pattern-provided substrate including forming a resist layer on a substrate, forming an opening corresponding to a circuit pattern and having an eaves cross-sectional shape in the resist layer, forming a thin film layer having a portion formed on the substrate in the opening and a portion formed on the resist layer, and removing the resist layer such that the resist layer and the portion of the thin film layer formed on the resist layer are removed from the substrate. The forming of the opening comprises exposing the resist layer with a mask device which changes an exposure amount of the resist layer such that the eaves cross-sectional shape has a space at a boundary between the resist layer and the substrate.
Public/Granted literature
- US20090205851A1 ELECTRONIC CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME Public/Granted day:2009-08-20
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