Invention Grant
US08420411B2 Method for aligning wafer stack 有权
对准晶片堆叠的方法

  • Patent Title: Method for aligning wafer stack
  • Patent Title (中): 对准晶片堆叠的方法
  • Application No.: US13326330
    Application Date: 2011-12-15
  • Publication No.: US08420411B2
    Publication Date: 2013-04-16
  • Inventor: Shing-Hwa Renn
  • Applicant: Shing-Hwa Renn
  • Applicant Address: TW Kueishan, Tao-Yuan Hsien
  • Assignee: Nanya Technology Corp.
  • Current Assignee: Nanya Technology Corp.
  • Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
  • Agent Winston Hsu; Scott Margo
  • Main IPC: H01L21/00
  • IPC: H01L21/00
Method for aligning wafer stack
Abstract:
A method for aligning a wafer stack includes providing a wafer stack including a top wafer with a top mark and a bottom wafer with a bottom mark in particular the top mark and the bottom mark capable of corresponding to each other; adjusting a relative position between the top wafer and the bottom wafer so that the top mark and the bottom mark are in contact with each other; applying an electrical signal on the top mark to obtain an electrical reading and optimizing the electrical reading to substantially align the wafer stack.
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