Invention Grant
US08420518B2 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
有权
在CMOS电路中通过晶片通孔放置的闭锁稳健性的结构和方法
- Patent Title: Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
- Patent Title (中): 在CMOS电路中通过晶片通孔放置的闭锁稳健性的结构和方法
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Application No.: US13095158Application Date: 2011-04-27
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Publication No.: US08420518B2Publication Date: 2013-04-16
- Inventor: Phillip F. Chapman , David S. Collins , Steven H. Voldman
- Applicant: Phillip F. Chapman , David S. Collins , Steven H. Voldman
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Richard Kotulak
- Main IPC: H01L21/22
- IPC: H01L21/22
Abstract:
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
Public/Granted literature
- US20110198703A1 STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY Public/Granted day:2011-08-18
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