Invention Grant
- Patent Title: Manufacturing method of semiconductor device
- Patent Title (中): 半导体器件的制造方法
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Application No.: US11516273Application Date: 2006-09-06
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Publication No.: US08420546B2Publication Date: 2013-04-16
- Inventor: Ichiro Uehara , Hideomi Suzawa
- Applicant: Ichiro Uehara , Hideomi Suzawa
- Applicant Address: JP
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP
- Agency: Husch Blackwell LLP
- Priority: JP2001-234285 20010801
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/461

Abstract:
In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist such as diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lov, area to a desired dimensional range so that the dimension thereof becomes larger.
Public/Granted literature
- US20070155182A1 Manufacturing method of semiconductor device Public/Granted day:2007-07-05
Information query
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