A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices. A semiconductor structure includes a UV cured tensile nitride layer formed over the substrate and between gate structures of the NFET devices, with portions of the UV cured tensile nitride layer having a trapezoidal profile with a bottom end wider than a top end.