Invention Grant
US08421222B2 Chip package having a chip combined with a substrate via a copper pillar
有权
具有通过铜柱与基板结合的芯片的芯片封装
- Patent Title: Chip package having a chip combined with a substrate via a copper pillar
- Patent Title (中): 具有通过铜柱与基板结合的芯片的芯片封装
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Application No.: US13207350Application Date: 2011-08-10
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Publication No.: US08421222B2Publication Date: 2013-04-16
- Inventor: Mou-Shiung Lin , Shih-Hsiung Lin, I
- Applicant: Mou-Shiung Lin , Shih-Hsiung Lin, I
- Applicant Address: TW Hsinchu
- Assignee: Megica Corporation
- Current Assignee: Megica Corporation
- Current Assignee Address: TW Hsinchu
- Agency: Seyfarth Shaw LLP
- Priority: TW91125126A 20021025
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L21/00
Abstract:
A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.
Public/Granted literature
- US20110291275A1 METHOD OF ASSEMBLING CHIPS Public/Granted day:2011-12-01
Information query
IPC分类:
