Provided is a semiconductor chip having a double bump structure. The semiconductor chip may include a semiconductor substrate, a circuit region on a surface of the semiconductor substrate, a pad on the semiconductor substrate and connected to the circuit region, a first bump on the pad, and a second bump on the first bump. The second bump may be arranged at one side of an upper surface of the first bump and the upper surface of the first bump may include a test area configured to interface with a probe tip, wherein the test area is an area of the upper surface of the first bump exposed by the second bump.