Invention Grant
- Patent Title: System and method for stacking a plurality of electrically coupled semiconductor chips with a conductive pin
- Patent Title (中): 用导电引脚堆叠多个电耦合的半导体芯片的系统和方法
-
Application No.: US12259100Application Date: 2008-10-27
-
Publication No.: US08421241B2Publication Date: 2013-04-16
- Inventor: Kouichi Meghro , Junichi Kasai
- Applicant: Kouichi Meghro , Junichi Kasai
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Priority: JP2007-277998 20071025
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of semiconductor devices can be mechanically and electrically coupled to each other.
Public/Granted literature
- US20090289336A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF Public/Granted day:2009-11-26
Information query
IPC分类:
