Invention Grant
- Patent Title: Substrate with embedded stacked through-silicon via die
- Patent Title (中): 基板通过芯片嵌入堆叠通硅
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Application No.: US12977030Application Date: 2010-12-22
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Publication No.: US08421245B2Publication Date: 2013-04-16
- Inventor: Javier Soto Gonzalez , Houssam Jomaa
- Applicant: Javier Soto Gonzalez , Houssam Jomaa
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.
Public/Granted literature
- US20120161316A1 SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE Public/Granted day:2012-06-28
Information query
IPC分类: